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<title>Memory segmentation</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Memory segmentation</span></span>

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</style><div role="note" class="hatnote navigation-not-searchable">This article is about segmented computer memory. For segments in object code, see <a href="Object_file" title="Object file">Object file</a>.</div>

<p>

<b>Memory segmentation</b> is an <a href="Operating_system" title="Operating system">operating system</a> <a href="Memory_management_(operating_systems)" title="Memory management (operating systems)">memory management</a> technique of dividing a <a href="Computer" title="Computer">computer</a>'s <a href="Primary_memory" class="mw-redirect" title="Primary memory">primary memory</a> into <b>segments</b> or <b>sections</b>. In a <a href="Computer_architecture" title="Computer architecture">computer system</a> using segmentation, a reference to a memory location includes a value that identifies a segment and an <a href="Offset_(computer_science)" title="Offset (computer science)">offset</a> (memory location) within that segment. Segments or sections are also used in <a href="Object_file" title="Object file">object files</a> of compiled programs when they are <a href="Linker_(computing)" title="Linker (computing)">linked</a> together into a <a href="Program_image" class="mw-redirect" title="Program image">program image</a> and when the image is <a href="Loader_(computing)" title="Loader (computing)">loaded</a> into memory.

</p><p>Segments usually correspond to natural divisions of a program such as individual routines or data tables<sup id="cite_ref-holt1961_1-0" class="reference"><a href="#cite_note-holt1961-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> so segmentation is generally more visible to the programmer than <a href="Paging" class="mw-redirect" title="Paging">paging</a> alone.<sup id="cite_ref-englander_2-0" class="reference"><a href="#cite_note-englander-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Segments may be created for program <a href="Module_(programming)" class="mw-redirect" title="Module (programming)">modules</a>, or for classes of memory usage such as <a href="Code_segment" title="Code segment">code segments</a> and <a href="Data_segment" title="Data segment">data segments</a>.<sup id="cite_ref-glaser1965_3-0" class="reference"><a href="#cite_note-glaser1965-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Certain segments may be shared between programs.<sup id="cite_ref-holt1961_1-1" class="reference"><a href="#cite_note-holt1961-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-englander_2-1" class="reference"><a href="#cite_note-englander-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>

</p><p>Segmentation was originally invented as a method by which <a href="System_software" title="System software">system software</a> could isolate software <a href="Process_(computing)" title="Process (computing)">processes</a> (<a href="Task_(computing)" title="Task (computing)">tasks</a>) and data they are using. It was intended to increase reliability of the systems running multiple processes simultaneously.<sup id="cite_ref-:0_4-0" class="reference"><a href="#cite_note-:0-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading2"><h2 id="Hardware_implementation">Hardware implementation</h2></div>

<p>In a system using segmentation, computer memory addresses consist of a segment id and an offset within the segment.<sup id="cite_ref-glaser1965_3-1" class="reference"><a href="#cite_note-glaser1965-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> A hardware <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) is responsible for translating the segment and offset into a <a href="Physical_address" title="Physical address">physical address</a>, and for performing checks to make sure the translation can be done and that the reference to that segment and offset is permitted.

</p><p>Each segment has a length and set of permissions (for example, <i>read</i>, <i>write</i>, <i>execute</i>) associated with it.<sup id="cite_ref-glaser1965_3-2" class="reference"><a href="#cite_note-glaser1965-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> A <a href="Process_(computing)" title="Process (computing)">process</a> is only allowed to make a reference into a segment if the type of reference is allowed by the permissions, and if the offset within the segment is within the range specified by the length of the segment. Otherwise, a <a href="Hardware_exception" class="mw-redirect" title="Hardware exception">hardware exception</a> such as a <a href="Segmentation_fault" title="Segmentation fault">segmentation fault</a> is raised.

</p><p>Segments may also be used to implement <a href="Virtual_memory" title="Virtual memory">virtual memory</a>. In this case each segment has an associated flag indicating whether it is present in main memory or not. If a segment is accessed that is not present in main memory, an exception is raised, and the <a href="Operating_system" title="Operating system">operating system</a> will read the segment into memory from secondary storage.

</p><p>Segmentation is one method of implementing <a href="Memory_protection" title="Memory protection">memory protection</a>.<sup id="cite_ref-ostep-1_5-0" class="reference"><a href="#cite_note-ostep-1-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> <a href="Page_(computer_memory)" title="Page (computer memory)">Paging</a> is another, and they can be combined. The size of a memory segment is generally not fixed and may be as small as a single <a href="Byte" title="Byte">byte</a>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>

</p><p>Segmentation has been implemented several ways on various hardware, with or without paging. Intel <a href="X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a> does not fit either model and is discussed separately below, and also in greater detail in a separate article.

</p>

<div class="mw-heading mw-heading3"><h3 id="Segmentation_without_paging">Segmentation without paging</h3></div>

<p>Associated with each segment is information that indicates where the segment is located in memory— the <i>segment base</i>. When a program references a memory location, the offset is added to the segment base to generate a physical memory address.

</p><p>An implementation of virtual memory on a system using segmentation without paging requires that entire segments be swapped back and forth between main memory and secondary storage. When a segment is swapped in, the operating system has to allocate enough contiguous free memory to hold the entire segment. Often <a href="Fragmentation_(computing)" title="Fragmentation (computing)">memory fragmentation</a> results if there is not enough contiguous memory even though there may be enough in total.

</p>

<div class="mw-heading mw-heading3"><h3 id="Segmentation_with_paging">Segmentation with paging</h3></div>

<p>Instead of a memory location, the segment information includes the address of a <a href="Page_table" title="Page table">page table</a> for the segment.

When a program references a memory location the offset is translated to a memory address using the page table. A segment can be extended by allocating another memory page and adding it to the segment's page table.

</p><p>An implementation of <a href="Virtual_memory" title="Virtual memory">virtual memory</a> on a system using segmentation with paging usually only moves individual pages back and forth between main memory and secondary storage, similar to a paged non-segmented system. Pages of the segment can be located anywhere in main memory and need not be contiguous. This usually results in a reduced amount of input/output between primary and secondary storage and reduced memory fragmentation.

</p>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>The <a href="Burroughs_Corporation" title="Burroughs Corporation">Burroughs Corporation</a> <a href="Burroughs_large_systems" class="mw-redirect" title="Burroughs large systems">B5000</a> computer was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory"<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> based on segmentation. The B5000 is equipped with a segment information table called the Program Reference Table (PRT) which is used to indicate whether the corresponding segment resides in the main memory, to maintain the <a href="Base_address" title="Base address">base address</a> and the size of the segment.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> The later <a href="Burroughs_large_systems" class="mw-redirect" title="Burroughs large systems">B6500</a> computer also implemented segmentation; a version of its architecture is still in use today on the Unisys ClearPath Libra servers.

</p><p>The <a href="GE_645" title="GE 645">GE 645</a> computer, a modification of the <a href="GE-600_series" title="GE-600 series">GE-635</a> with segmentation and paging support added, was designed in 1964 to support <a href="Multics" title="Multics">Multics</a>.

</p><p>The <a href="Intel_iAPX_432" title="Intel iAPX 432">Intel iAPX 432</a>,<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor.

</p><p>The 960MX version of the <a href="Intel_i960" title="Intel i960">Intel i960</a> processors supported load and store instructions with the source or destination being an "access descriptor" for an object, and an offset into the object, with the access descriptor being in a 32-bit register and with the offset computed from a base offset in the next register and from an additional offset and, optionally, an index register specified in the instruction. An access descriptor contains permission bits and a 26-bit object index; the object index is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the object type.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup>

</p><p><a href="Prime_Computer" title="Prime Computer">Prime</a>, <a href="Stratus_Technologies" title="Stratus Technologies">Stratus</a>, <a href="Apollo_Computer" title="Apollo Computer">Apollo</a>, <a href="IBM_System/38" title="IBM System/38">IBM System/38</a>, and <a href="IBM_AS/400" title="IBM AS/400">IBM AS/400</a> (including <a href="IBM_i" title="IBM i">IBM i</a>) computers use memory segmentation.

</p>

<div class="mw-heading mw-heading2"><h2 id="Examples">Examples</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Burroughs_large_system_architectures"><a href="Burroughs_Large_Systems" title="Burroughs Large Systems">Burroughs large system architectures</a></h3></div>

<div role="note" class="hatnote navigation-not-searchable">See also: <a href="Burroughs_large_systems_descriptors" title="Burroughs large systems descriptors">Burroughs large systems descriptors</a></div>

<p>Burroughs introduced segmentation on the <a href="B5000" class="mw-redirect" title="B5000">B5000</a>, followed by the compatible B5500 and B5700.

</p><p>The later <a href="B6500" class="mw-redirect" title="B6500">B6500</a> replaced the Program Reference Table (PRT) with a <a href="Saguaro_stack" class="mw-redirect" title="Saguaro stack">Saguaro stack</a>, changed control word formats, changed <a href="Burroughs_large_systems_descriptors" title="Burroughs large systems descriptors">descriptor</a> formats and changed the mechanism for referring to a control word or descriptor.

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<div role="note" class="hatnote navigation-not-searchable">See also: <a href="B5000_instruction_set" title="B5000 instruction set">B5000 instruction set</a> and <a href="Burroughs_large_systems_descriptors#B5000,_B5500_and_B5700" title="Burroughs large systems descriptors">Burroughs large systems descriptors § B5000, B5500 and B5700</a></div>

<p>Words in the <a href="Burroughs_Large_Systems#B5000,_B5500,_and_B5700" title="Burroughs Large Systems">B5000, B5500 and B5700</a> are 48 bits long.<sup id="cite_ref-oper_11-0" class="reference"><a href="#cite_note-oper-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> <a href="Burroughs_large_systems_descriptors" title="Burroughs large systems descriptors">Descriptors</a> have the uppermost bit set in the word. They reside in either the Program Reference Table (PRT) or the stack, and contain a <i>presence bit</i> indicating whether the data are present in memory. There are distinct data and program descriptors.<sup id="cite_ref-oper_11-1" class="reference"><a href="#cite_note-oper-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 4-2–4-4">: 4-2–4-4 </span></sup>

</p>

<div class="mw-heading mw-heading4"><h4 id="B6500,_B7500_and_successors">B6500, B7500 and successors</h4></div>

<div role="note" class="hatnote navigation-not-searchable">See also: <a href="Burroughs_B6x00-7x00_instruction_set" title="Burroughs B6x00-7x00 instruction set">Burroughs B6x00-7x00 instruction set</a> and <a href="Burroughs_large_systems_descriptors#B6500,_B7500_and_successors" title="Burroughs large systems descriptors">Burroughs large systems descriptors § B6500, B7500 and successors</a></div>

<p>Words in the B6500 and its successors have 48 bits of data and 3 tag bits.<sup id="cite_ref-b6500-ref-man_12-0" class="reference"><a href="#cite_note-b6500-ref-man-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 2-1">: 2-1 </span></sup> The tag bits indicate the type of data contained in the word; there are several descriptor types, indicated by different tag bit values.<sup id="cite_ref-b6500-ref-man_12-1" class="reference"><a href="#cite_note-b6500-ref-man-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 6-5–6-10">: 6-5–6-10 </span></sup> Control words and descriptors reside in the Saguaro stack. Array segments may be paged.

</p><p>The line includes the B6500, B6700, B7700, B6800, B6900, B5900, the A-series Burroughs and Unisys machines, and the current Clearpath MCP systems (Libra). While there have been a few enhancements over the years, particularly hardware advances, the architecture has changed little. The segmentation scheme has remained the same, see <a href="Virtual_Memory" class="mw-redirect" title="Virtual Memory">Segmented memory</a>.

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<div class="mw-heading mw-heading3"><h3 id="Multics_architectures">Multics architectures</h3></div>

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<div class="mw-heading mw-heading3"><h3 id="S/370_architecture">S/370 architecture</h3></div>

<p>In the <a href="IBM_System/370" title="IBM System/370">IBM System/370</a> models<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> with virtual storage<sup id="cite_ref-S370_14-0" class="reference"><a href="#cite_note-S370-14"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-S370-10_15-0" class="reference"><a href="#cite_note-S370-10-15"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> (DAT) and 24-bit addresses, <a href="Control_register" title="Control register">control register</a> 0 specifies a segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 contains a Segment Table Designator (STD), which specifies the length and real address of the segment table. Each segment table entry contains a page table location, a page table length and an invalid bit. IBM later expanded the address size to 31 bits and added two bits to the segment table entries:

</p>

<dl><dt>Segment-protection bit</dt>

<dd>Segment is read-only</dd>

<dt>Common-segment bit</dt>

<dd>The segment is shared between address spaces; this bit is set to optimize TLB use</dd></dl>

<p>Each of IBM's DAT implementations includes a translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model.

</p><p>Starting with the <a href="IBM_303X" title="IBM 303X">3031, 3032, and 3033</a> processor complexes, IBM offered a feature called <i>Dual-address Space</i><sup id="cite_ref-S370-10_15-1" class="reference"><a href="#cite_note-S370-10-15"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 5-13–5-17, Dual-Address-Space Control">: 5-13–5-17, Dual-Address-Space Control </span></sup><sup class="reference nowrap"><span title="Pages: 5-17–5-20, DAS Authorization Mechanisms">: 5-17–5-20, DAS Authorization Mechanisms </span></sup><sup class="reference nowrap"><span title="Pages: 5-21–5-24, PC-Number Translation">: 5-21–5-24, PC-Number Translation </span></sup><sup id="cite_ref-S370-XA_16-0" class="reference"><a href="#cite_note-S370-XA-16"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> (DAS), which allows a program to switch between the translation tables for two address spaces, referred to as <i>primary address space</i> (CR1) and <i>secondary address space</i> (CR7), and to move data between the address spaces subject to protection key. DAS supports a translation table to convert a 16-bit address space number (ASN) to an STD, with privileged instructions to load the STD into CR1 (primary) or CR7 (secondary).

</p>

<div class="mw-heading mw-heading3"><h3 id="x86_architecture">x86 architecture</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a></div>

<p>Early <a href="X86" title="X86">x86</a> processors, beginning with the <a href="Intel_8086" title="Intel 8086">Intel 8086</a>, provide crude memory segmentation and no <a href="Memory_protection" title="Memory protection">memory protection</a>. (Every byte of every segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at a fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64 KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64 KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1 MiB (1024 KiB) of physical memory (and memory-mapped i/o). (Optional <a href="Expanded_memory" title="Expanded memory">expanded memory</a> hardware can add bank-switched memory under software control.) Intel retroactively named the sole operating mode of these x86 CPU models "<a href="Real_mode" title="Real mode">real mode</a>".

</p><p>The <a href="Intel_80286" title="Intel 80286">Intel 80286</a> and later processors add "286 <a href="Protected_mode" title="Protected mode">protected mode</a>", which retains 16-bit addressing, and adds segmentation (without paging) and per-segment memory protection. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64 KiB segments, no memory protection, only 1 MiB physical address space, and some subtle differences (<a href="High_memory_area" title="High memory area">high memory area</a>, <a href="Unreal_mode" title="Unreal mode">unreal mode</a>). In order to use its full 24-bit (16 MiB) physical address space and advanced <a href="Memory_management_unit" title="Memory management unit">MMU</a> features, an 80286 or later processor must be switched into "protected mode" by software, usually the operating system or a <a href="DOS_extender" title="DOS extender">DOS extender</a>. If a program does not use the segment registers, or only puts values into them that it receives from the operating system, then identical code can run in real mode or protected mode, but most real-mode software computes new values for the segment registers, breaking this compatibility.

</p><p>The <a href="Intel_i386" class="mw-redirect" title="Intel i386">Intel i386</a> and later processors add "386 <a href="Protected_mode" title="Protected mode">protected mode</a>", which uses 32-bit addressing, retains segmentation, and adds <a href="Memory_paging" title="Memory paging">memory paging</a>. In these processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in <i>linear memory</i>. When paging is enabled, addresses in linear memory are then mapped to physical addresses using a separate page table. Most operating systems did not use the segmentation capability, opting to keep the base address in all segment registers equal to 0 at all times and provide per-page memory protection and swapping using only paging. Some use the CS register to provide <a href="Executable_space_protection" class="mw-redirect" title="Executable space protection">executable space protection</a> on processors lacking the <a href="NX_bit" title="NX bit">NX bit</a> or use the FS or GS registers to access thread-local storage.<sup id="cite_ref-pietrek-windows-nt_17-0" class="reference"><a href="#cite_note-pietrek-windows-nt-17"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-drepper-linux-etc_18-0" class="reference"><a href="#cite_note-drepper-linux-etc-18"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</p><p>The <a href="X86-64" title="X86-64">x86-64</a> architecture does not support segmentation in "<a href="Long_mode" title="Long mode">long mode</a>" (64-bit mode).<sup id="cite_ref-:1_19-0" class="reference"><a href="#cite_note-:1-19"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 2<sup>64</sup>. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes such as thread-local storage.<sup id="cite_ref-pietrek-windows-nt_17-1" class="reference"><a href="#cite_note-pietrek-windows-nt-17"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-drepper-linux-etc_18-1" class="reference"><a href="#cite_note-drepper-linux-etc-18"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</p>

<ul><li><a href="BSS_Segment" class="mw-redirect" title="BSS Segment">BSS Segment</a></li>

<li><a href="Data_segment" title="Data segment">Data segment</a></li>

<li><a href="Flat_memory_model" title="Flat memory model">Flat memory model</a></li>

<li><a href="Memory_management_(operating_systems)" title="Memory management (operating systems)">Memory management (operating systems)</a></li>

<li><a href="Segmentation_fault" title="Segmentation fault">Segmentation fault</a></li>

<li><a href="Virtual_address_space" title="Virtual address space">Virtual address space</a></li>

<li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

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<li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text">Models 115, 125, 135, 138, 145, 148, 155 II, 158, 165 II, and 168</span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFHolt1961" class="citation journal cs1">Holt, Anatol W. (1961). <a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F366786.366795">"Program Organization and Record Keeping for Dynamic Storage Allocation"</a>. <i>Communications of the ACM</i>. <b>4</b> (10): <span class="nowrap">422–</span>431. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F366786.366795">10.1145/366786.366795</a></span>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:18973700">18973700</a>.</cite></span>

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<li id="cite_note-ostep-1-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-ostep-1_5-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFArpaci-DusseauArpaci-Dusseau2014" class="citation book cs1">Arpaci-Dusseau, Remzi H.; Arpaci-Dusseau, Andrea C. (2014). <a rel="nofollow" class="external text" href="http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf">"Segmentation"</a> <span class="cs1-format">(PDF)</span>. <i>Operating Systems: Three Easy Pieces</i>. Arpaci-Dusseau Books.</cite></span>

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<li id="cite_note-oper-11"><span class="mw-cite-backlink">^ <a href="#cite_ref-oper_11-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-oper_11-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://bitsavers.org/pdf/burroughs/LargeSystems/B5000_5500_5700/5000-21005_B5000_operChar_1963.pdf"><i>The Operational Characteristic of the Processors for the Burroughs B 5000</i></a> <span class="cs1-format">(PDF)</span> (A ed.), Detroit: Burroughs, 1962, 5000-21005A</cite></span>

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</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li>IA-32 Intel Architecture Software Developer’s Manual Volume 3A: System Programming Guide. <a rel="nofollow" class="external free" href="http://www.intel.com/products/processor/manuals/index.htm">http://www.intel.com/products/processor/manuals/index.htm</a>.</li>

<li>Operating Systems: Internals and Design Principles by William Stallings. Publisher: Prentice Hall. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-13-147954-7</bdi>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-13-147954-8</bdi>.</li></ul>

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</style><div id="Memory_management1048" style="font-size:114%;margin:0 4em"><a href="Memory_management" title="Memory management">Memory management</a></div></th></tr><tr><td class="navbox-abovebelow" colspan="2"><div>

<ul><li><a href="Memory_management_(operating_systems)" title="Memory management (operating systems)">Memory management as a function of an operating system</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)</li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li>

<li><a href="Input%E2%80%93output_memory_management_unit" title="Input–output memory management unit">Input–output memory management unit</a> (IOMMU)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Demand_paging" title="Demand paging">Demand paging</a></li>

<li><a href="Memory_paging" title="Memory paging">Memory paging</a></li>

<li><a href="Page_table" title="Page table">Page table</a></li>

<li><a href="Virtual_memory_compression" title="Virtual memory compression">Virtual memory compression</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Protected_mode" title="Protected mode">Protected mode</a></li>

<li><a href="Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a></li>

<li><a href="X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Memory_allocator" class="mw-redirect" title="Memory allocator">Allocator</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Dlmalloc" class="mw-redirect" title="Dlmalloc">dlmalloc</a></li>

<li><a href="Hoard_memory_allocator" title="Hoard memory allocator">Hoard</a></li>

<li><a href="Jemalloc" class="mw-redirect" title="Jemalloc">jemalloc</a></li>

<li><a href="Libumem" title="Libumem">libumem</a></li>

<li><a href="Mimalloc" title="Mimalloc">mimalloc</a></li>

<li><a href="Ptmalloc" class="mw-redirect" title="Ptmalloc">ptmalloc</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Manual_memory_management" title="Manual memory management">Manual</a> means</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Static_variable" title="Static variable">Static memory allocation</a></li>

<li><a href="C_dynamic_memory_allocation" title="C dynamic memory allocation">C dynamic memory allocation</a></li>

<li><a href="New_and_delete_(C%2B%2B)" title="New and delete (C++)">new and delete (C++)</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Garbage_collection_(computer_science)" title="Garbage collection (computer science)">Garbage<br>collection</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Automatic_Reference_Counting" title="Automatic Reference Counting">Automatic Reference Counting</a></li>

<li><a href="Boehm_garbage_collector" title="Boehm garbage collector">Boehm garbage collector</a></li>

<li><a href="Cheney's_algorithm" title="Cheney's algorithm">Cheney's algorithm</a></li>

<li><a href="Concurrent_mark_sweep_collector" title="Concurrent mark sweep collector">Concurrent mark sweep collector</a></li>

<li><a href="Finalizer" title="Finalizer">Finalizer</a></li>

<li><a href="Garbage_(computer_science)" title="Garbage (computer science)">Garbage</a></li>

<li><a href="Garbage-first_collector" title="Garbage-first collector">Garbage-first collector</a></li>

<li><a href="Mark%E2%80%93compact_algorithm" title="Mark–compact algorithm">Mark–compact algorithm</a></li>

<li><a href="Reference_counting" title="Reference counting">Reference counting</a></li>

<li><a href="Tracing_garbage_collection" title="Tracing garbage collection">Tracing garbage collection</a></li>

<li><a href="Weak_reference" title="Weak reference">Strong reference</a></li>

<li><a href="Weak_reference" title="Weak reference">Weak reference</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Memory_safety" title="Memory safety">Safety</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Buffer_overflow" title="Buffer overflow">Buffer overflow</a></li>

<li><a href="Buffer_over-read" title="Buffer over-read">Buffer over-read</a></li>

<li><a href="Dangling_pointer" title="Dangling pointer">Dangling pointer</a></li>

<li><a href="Stack_overflow" title="Stack overflow">Stack overflow</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Issues</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Fragmentation_(computing)" title="Fragmentation (computing)">Fragmentation</a></li>

<li><a href="Memory_leak" title="Memory leak">Memory leak</a></li>

<li><a href="Unreachable_memory" title="Unreachable memory">Unreachable memory</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Automatic_variable" title="Automatic variable">Automatic variable</a></li>

<li><a href="International_Symposium_on_Memory_Management" title="International Symposium on Memory Management">International Symposium on Memory Management</a></li>

<li><a href="Region-based_memory_management" title="Region-based memory management">Region-based memory management</a></li>

<li><a href="Memory_pool" title="Memory pool">Memory pool</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>

<ul><li><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Memory management</li>

<li><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Virtual memory</li>

<li><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Automatic memory management</li>

<li><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Memory management algorithms</li>

<li><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Memory management software</li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Application_binary_interface_(ABI)74" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Application_binary_interface_(ABI)74" style="font-size:114%;margin:0 4em"><a href="Application_binary_interface" title="Application binary interface">Application binary interface</a> (ABI)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Parts,<br>conventions</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_structure_alignment" title="Data structure alignment">Alignment</a></li>

<li><a href="Calling_convention" title="Calling convention">Calling convention</a></li>

<li><a href="Call_stack" title="Call stack">Call stack</a></li>

<li><a href="Library_(computing)" title="Library (computing)">Library</a>

<ul><li><a href="Static_library" title="Static library">static</a></li></ul></li>

<li><a href="Machine_code" title="Machine code">Machine code</a></li>

<li><a href="Name_mangling" title="Name mangling">Name mangling</a></li>

<li><a href="Object_code" title="Object code">Object code</a></li>

<li><a href="Opaque_pointer" title="Opaque pointer">Opaque pointer</a></li>

<li><a href="Position-independent_code" title="Position-independent code">Position-independent code</a></li>

<li><a href="Relocation_(computing)" title="Relocation (computing)">Relocation</a></li>

<li><a href="System_call" title="System call">System call</a></li>

<li><a href="Virtual_method_table" title="Virtual method table">Virtual method table</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related topics</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Binary-code_compatibility" title="Binary-code compatibility">Binary-code compatibility</a></li>

<li><a href="Foreign_function_interface" title="Foreign function interface">Foreign function interface</a></li>

<li><a href="Language_binding" title="Language binding">Language binding</a></li>

<li><a href="Linker_(computing)" title="Linker (computing)">Linker</a>

<ul><li><a href="Dynamic_linker" title="Dynamic linker">dynamic</a></li></ul></li>

<li><a href="Loader_(computing)" title="Loader (computing)">Loader</a></li>

<li><a href="Year_2038_problem" title="Year 2038 problem">Year 2038 problem</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-07-28" href="https://en.wikipedia.org/wiki/?title=Memory_segmentation&oldid=1302923819">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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